In a metal-oxide-semiconductor field-effect transistor (MOS FET), the on resistance increases with an increase in the contact resistance between a source electrode, and a surface of a source region and a surface of a p well region. The relationship between the contact resistance and the impurity concentration of silicon is disclosed in A.Y.C.Yu, Electron Tunneling and Contact Resistance of Metal-Silicon Contact Barriers, Solid State Electronics, 13, p279, 1970, and VLSI process data handbook p319 (Science Forum), for example.
FIGS. 16(a) and 16(b) show the dependence of the contact resistance of aluminum (Al) and silicon upon the impurity concentration, wherein FIG. 16(a) indicates the case where n-type silicon is used, and FIG. 16(b) indicates the case where p-type silicon is used. In FIG. 16(a), the contact resistance can be reduced to 10.sup.-6 .OMEGA. cm.sup.2 or lower by controlling the impurity concentration (donor concentration) to be 10.sup.20 cm.sup.-3 or higher. If the impurity concentration is reduced by one order of magnitude, i.e., to 10.sup.19 cm.sup.-3, however, the contact resistance, which greatly depends on the impurity concentration, increases by six orders of magnitude (10.sup.6 times) to 1 .OMEGA. cm.sup.2. In FIG. 16(b), the contact resistance may be reduced to 10.sup.-6 .OMEGA. cm.sup.2 or lower by controlling the impurity concentration (acceptor concentration) to be only about 5.times.10.sup.18 .OMEGA. cm.sup.-3. Thus, in order to control the contact resistance of a MOSFET to be 10.sup.-6 .OMEGA. cm.sup.2 or lower, for example, the surface concentration of its n source region needs to be controlled to be 10.sup.20 cm.sup.-3 or higher, and the surface concentration of its p well region needs to be controlled to be 5.times.10.sup.18 cm or higher.
FIG. 17 shows a first known example of manufacturing method for reducing the contact resistance, wherein (a) through (f) are process steps to be taken in this order in this method. In the step (a), an n-type region 2a and a p-type region 3a are formed in a semiconductor region 60, and surfaces of these regions 2a, 3a, 60 are covered with an oxide film 4. In the step (b), the oxide film 4 is covered with a photoresist film (hereinafter referred to simply as "resist film) that is not shown in the figure, and selected portions of the oxide film 4 are removed by etching, using this resist film as a mask, so as to form contact holes 5. The resist film is then removed. In the step (c), a resist film 6 is formed over the entire surface of the structure obtained in the step (b), and a portion of the resist film 6 that is located on the n-type region 2a is removed so that the other portion of the film 6 that is not on the n-type region 2a remains on the structure. In the step (d), ionized n-type impurity atoms (indicated by arrows 7) are implanted using the resist film 5 as a mask exclusively used for forming an n-type impurity region 15a. In the step (e), the resist film 6 is removed and heat treatment is carried out, so that the high-concentration n-type impurity region 15a that provides an n-type contact region is formed in a surface layer of the n-type region 2a. In the step (f), metal wiring layers or conductive layers 9 are secured to the n-type contact region provided by the high-concentration n-type impurity region 15a, and a p-type contact region formed at the surface of the p-type region 3a.
FIG. 18 shows a second known example of manufacturing method for reducing the contact resistance, wherein (a) through (f) are process steps to be taken in this order. In this known method, the contact resistance is reduced by securing a metal wiring layer to both an n-type region and a p-type region. In the step (a) of FIG. 18, an oxide film 4 is formed on a semiconductor region 60, and an opening is provided in the oxide film 4. Ions of p-type impurity atoms are then implanted into the semiconductor region 60, using the oxide film 4 as a mask exclusively used for forming a p-type region 3b that provides a p-type contact region . In the step (b), an oxide film 4g is formed in the opening of the oxide film 4. In the step (c), an opening is provided in the oxide films 4, 4g, and an n-type region 2b that provides an n-type contact region is formed adjacent to the p-type region 3b, using these oxide films 4, 4g as an exclusive mask for forming the region 2b. In the step (d), an oxide film 4h is formed in the opening by thermal oxidation or CVD method. In the step (e), an opening is provided in the oxide film 4h, so as to form a contact hole 5. In the step (f), a metal wiring layer or conductive layer 9 is secured to the surface of the n-type region 2b that provides the n-type contact region, and to the surface of the p-type region 3b that provide the p-type contact region.
In either of the known examples of FIGS. 17 and 18, the ion implantation steps for forming the n-type contact region and the p-type contact region require respective photolithography steps using exclusive masks for forming these contact regions. This undesirably increases the manufacturing cost. In addition, errors in matching these exclusive masks, namely, positioning these masks relative to each other, in the photolithography steps may cause a deviation of the dimensions of the n-type contact region or p-type contact region from design values, or a deviation of the ratio of the sizes or areas of the n-type and p type contact regions from a design value, resulting in an increase in the contact resistance.